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Revision 1.4
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AS5132
Datasheet - Detailed Description
7.2.1   PWM External Clock
The PWM period depends on the setting of the OTP bit Ext. CLK EN. By default the internal clock source is used as a reference. An external
clock can be connected to the pin COM/INC.
In case Ext. CLK EN is set, the output-mode which is determined by the states of {COM/INC, Test3, Test2, Test1, Test0} (see Table 6) during
start-up is overwritten and U,V,W commutation mode signals are activated.
After internal power on reset (POR_en), the OTP is read out. When the Ext. CLK EN is programmed successfully, the COM/INC pin is used as
external clock for the PWM block. After 4 clock cycles of Ext. CLK EN, the reset of TADC (TADC_rst) and the PWM block is released.
Figure 14. Start-up Procedure
The reset for the PWM block is synchronized to the external PWM clock. This ensures a save reset also in case the external clock on COM/INC
is already running during start-up.
Figure 15. PWM Output Signal
Table 5. PWM Timing with Internal and External CLK Source
Symbol
Parameter
Min
Typ
Max
Unit
Note
T
PWMint
PWM Period internal
600
750
900
Internal clock source
T
PWMext
PWM Period external
383 / CLK
PWM
External clock provided over
COM / INC pin
CLK
PWM
Clock external mode
0
766
kHz
POR_en
system_state
Ext. CLK EN
TADC_rst
OTP_readout
RUN
258*Tclk_sys
4*Tclk_sys
Init (Error)
Zero degree
Angle Position
16 clocks
359 clocks
exit
8 clocks
T-high
T-low
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